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L6208
FULLY INTEGRATED STEPPER MOTOR DRIVER
PRELIMINARY DATA
s
OPERATING SUPPLY VOLTAGE FROM 8 TO 52V
s s s s
5A PEAK CURRENT (2.8A DC) RDS(ON) 0.3 TYP. VALUE @ Tj = 25 C BUILT-IN DECODING LOGIC BUILT-IN CONSTANT OFF-TIME PWM CURRENT CONTROL FAST/SLOW DECAY MODE SELECTION HIGH SIDE OVER CURRENT PROTECTION 5.6A TYP. CROSS CONDUCTION PROTECTION THERMAL SHUTDOWN OPERATING FREQUENCY UP TO 100KHz INTRINSIC FAST FREE WHEELING DIODES UVLO: UNDER VOLTAGE LOCKOUT
The logic inputs are CMOS/TTL and P compatible. The device also includes all the circuitry needed to drive a stepper motor, that is the constant off time PWM control that performs the chopping current control and the state machine that generates the stepping sequence. Other features are the protection of the high side switches against unsafe over current conditions and the thermal shutdown. The L6208 is assembled in PowerDIP24(20+2+2), PowerSO36 and SO24(20+2+2) packages.
PowerDIP24 PowerSO36 (20+2+2) ORDERING NUMBERS: L6208N L6208PD SO24 (20+2+2) L6208D
s s
s s s s s
DESCRIPTION The L6208 is a fully integrated stepper motor driver manufactured with multipower BCD technology, which combines isolated DMOS power transistors with CMOS and bipolar circuits on the same chip.
BLOCK DIAGRAM
OUT1A GND GND GND GND EN Reset Clock CW/CCW Vref B HALF/FULL Control Vref A
VS A
SENSEA
OUT2A
VS A
VS A
VS A
PWMA
RCA
Logic & Drivers
VBOOT Charge Pump VCP
PWMB
RCB
VS B VS B VS B
OUT1 B
SENSE B
OUT2B
VS B
January 2001
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change with out notice.
1/15
L6208
FUNCTIONAL BLOCK DIAGRAM
Vboot
Thermal Protection Voltage Regulator 10V Vboot 5V
VCP
Charge Pump Vboot Vboot
VSA
EN CONTROL HALF/FULL Clock RESET CW/CCW RCA Input Interface
Over Current Detection
10V 10V
OUT1A OUT2A
SENSE A Decoding Logic
One Shot
Masking Tim e
Sense Comparator
VrefA
PWM
BRIDGE A
VSB OUT1B RCB VrefB BRIDGE B OUT2B SENSE B
ABSOLUTE MAXIMUM RATINGS
Symbol VS VIN,V EN VrefA, VrefB V RCA,RCB V SENSE VBOOT IS(peak) Parameter Supply Voltage Input and Enable Voltage Range Voltage Range at Vref pins Voltage Range at RCA and RCB pins DC Sensing Voltage Range Bootstrap Peak Voltage Pulsed Supply Current (for each VS pin), internally limited by the overcurrent protection. DCvSupply Current (for each VS pin) Differential Voltage Between VS A, OUT1A, OUT2A, SENSEA and VS B, OUT1B, OUT2 B, SENSEB Storage and Operating Temperature Range tPULSE < 1ms Test conditio ns Value 60 -0.3 to +7 -0.3 to +7 -0.3 to +7 -1 to +4 V S + 10 7.1 Unit V V V V V V A
IS VOD
2.8 60
A V
Tstg, TOP
-40 to 150
C
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L6208
RECOMMENDED OPERATING CONDITIONS
Symbol VS VOD Supply Voltages Differential Voltage Between VS A, OUT1A, OUT2A, SENSEA and VS B, OUT1B, OUT2B, SENSEB Sensing voltage (pulsed twVSENSE
PIN CONNECTIONS (Top View)
GND NC NC Clock CW/CCW SENSEA RCA OUT1A GND GND OUT1B RCB SENSEB Vref B HALF/FULL 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 Vref A Reset VCP OUT2A VS A GND GND VS B OUT2B VBOOT EN Control VS A OUT2A NC VCP Reset Vref A Clock CW/CCW SENSEA RCA NC OUT1A NC NC GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 GND NC NC VS B OUT2B NC VBOOT EN Control HALF/FULL Vref B SENSEB RCB NC OUT1B NC NC GND
PDIP24/SO24
PowerSO36
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L6208
PIN DESCRIPTION
Name VS A VS B OUT1A OUT2A OUT1B OUT2B SENSE A SENSE B GND EN HALF/FULL PowerSO36 4 33 15 5 22 32 12 25 1, 18, 19, 36 29 27 PDIP24/ SO24 20 17 5 21 8 16 3 10 6, 7, 18, 19 14 12 Supply voltage of the bridge A. Supply voltage of the bridge B. Must be connected to VS A. Bridge A outputs. Function
Bridge B outputs.
Sense resistor for the bridge A. Sense resistor for the bridge B. Common ground terminals. In Powerdip and SO packages, these pins are also used for heat dissipation toward the PCB. Chip Enable. A Low logic level applied to this pin switches Off all the power DMOSs. Logic input. When high, HALF STEP operation is selected; a Low logic level selects FULL STEP operation. ONE-PHASE-ON FULL STEP MODE (wave mode) is obtained by selecting FULL when the state machine is at an even numbered state. TWO-PHASE-O N FULL STEP MODE (normal mode) is obtained by selecting FULL when the state machine is at an odd numbered state. Logic input. A Low logic level restores the home state (state 1) on the state machine. Logic input. Step Clock. The step occurs on the rising edge of this signal. Logic input. Logic High sets clockwise direction. Logic Low sets counterclockwise direction. Logic input. Selects chopping style. FAST DECAY is selected with logic Low. A logic High selects SLOW DECAY . A voltage applied to these pins sets the reference voltage of the sense comparators, determining the output current in PWM current control. Bootstrap oscillator. Oscillator output for the external charge pump. Supply voltage to overdrive the upper DMOSs. A parallel RC network connected to these pins sets the OFF time of the low-side power DMOS of the correspondent bridge. The pulse generator is a monostable triggered by the output of the sense comparator of the bridge (tOFF = 0.69 RC).
Reset Clock CW/CCW Control Vref A Vref B VCP VBOOT RCA RCB
8 10 11 28 9 26 7 30 13 24
23 1 2 13 24 11 22 15 4 9
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L6208
THERMAL DATA
Symbol R th-j-pins Description MaximumThermal Resistance Junction-Pins Maximum Thermal Resistance Junction-Case MaximumThermal Resistance Junction-Ambient (1) Maximum Thermal Resistance Junction-Ambient (2) PDIP24 18 SO24 14 PowerSO36 Unit C/W C/W C/W
R th-j-case
-
-
1
Rth-j-amb1
42
50
35
Rth-j-amb2
58
77
62
C/W
<(1)>Mounted on a multiplayer PCB with a dissipating copper surface on the bottom side of 2 x 12mm x 25mm (with a thickness of at least 35 m). <(2)>It's the same condition of the point above, without any heatsinking surface on the board.
ELECTRICAL CHARACTERISTICS (Tamb = 25 C, Vs = 48V, unless otherwise specified)
Symbol VS IS Tj Parameter Supply Voltage Quiescent Supply Current Thermal Shutdown Temperature All Bridges OFF 150 Test Conditions Min 8 5.5 Typ Max 52 10 Unit V mA C
Output DMOS Transistors I DSS RDS(ON) Leakage Current High-side Switch ON Resistance V S = 52V Tj = 25 C Tj =125 C Low-side Switch ON Resistance Tj = 25 C Tj =125 C Source Drain Diodes VSD trr t fr Forward ON Voltage Reverse Recovery Time Forward Recovery Time ISD = 2.8A, EN = LOW If = 2.8A 1.2 300 200 1.4 V ns ns 0.34 0.53 0.28 0.47 1 0.4 0.59 0.34 0.53 mA
Switching Rates tD(on) tON tD(OFF) tOFF tDCLK Output to out Turn ON Delay Time (3) Output Rise Time (3) Enable to out Turn OFF Delay Time (3) Output Fall Time (3) Clock to output delay time (3) ILOAD =2.8A ILOAD =2.8A ILOAD =2.8A ILOAD =2.8A ILOAD =2.8A 110 250 400 ns
20 240
105 580
300 760
ns ns
20
78 2
300
ns s
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L6208
ELECTRICAL CHARACTERISTICS (continued) (Tamb = 25 C, Vs = 48V, unless otherwise specified)
Symbol tdt tblank fCP Parameter Dead Time Protection Internal Blanking Time on SENSE pins Charge pump frequency Test Conditions Min Typ 1 1 0.75 1.5 1 Max Unit s s MHz
UVLO comp Vth(ON) Vth(OFF) Turn ON threshold Turn OFF threshold 6.6 5.6 7 6 7.4 6.4 s s
Logic Input VINL VINH IINH IINL tCLK tS tH tR tRCLK Low level logic input voltage High level logic input voltage High level logic input current Low level logic input current Minimum clock time (4) Minimum set up time (4) Minimum hold time (4) Minimum reset time (4) Minimum reset to clock delay (4) V IN, EN = 5 V V IN, EN = GND see Fig. 2 0.1 -0.3 2 0.8 7 70 -10 1 1 1 1 1 V V A A s s s s s
Over Current Protection IS OVER VDIAG Input supply over current protection threshold Open drain low level output voltage Tj = 25 C I = 4 mA 4 5.6 7.1 0.4 A V
Comparator and Monostable
IRCA, RCB Source current at RC pins
V RC=2.5 V
3 -0.1
5 5
Vref + 5mV
mA V
V ref Vth tprop tOFF Ibias
Input common mode comparator voltage range Comparator threshold voltage on SENSE pins Turn OFF propagation delay (5) PWMRecirculation time Input bias current at Vref pins V ref A, B = 0.5 V V ref A, B = 0.5 V 20 k < R < 100 k 0.1 nF < C < 100 nF
Vref - 5mV
0.1
0.2
0.3
s s A
0.67RC 0.69RC 0.71RC
0.2
<(3)>Resistive load used. See Fig. 1. <(4)>See Fig. 2. <(5)>Defined as the time between the voltage at the input of the current sense reaching the V ref threshold and the lower DMOS switch beginning to turn off. The voltage at SENSE pin is increased instantaneously from V ref -10 mV to Vref +10 mV.
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L6208
Figure 1. Switching Rates Definition
En
50 % t
IOUT 90 % 10 %
t
CLK
tD(OFF) tOFF tD(ON) t(ON)
50 % t
IOUT
t
tDCLK
Figure 2. Minimum Timing Definition
CLOCK tCLK
CLOCK
tCLK
Logic Inputs
tS
tH
RESET
tR
tRCLK
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L6208
Figure 3. Typical Quiescent Current vs. Supply Voltage
Iq [mA] 5.6
Figure 6. Typical High-Side RDS(ON) vs. Supply Voltage
RDS(ON) []
fc = 1kHz
Tj = 25C Tj = 85C Tj = 125C
0.380 0.376 0.372 0.368 0.364 0.360 0.356 0.352 0.348 0.344 0.340 0.336
5.4
Tj = 25C
5.2
5.0
4.8
4.6 0 10 20 30 V S [V] 40 50 60
0
5
10
15
V S [V]
20
25
30
Figure 4. Normalized Typical Quiescent Current vs. Switching Frequency
Iq / (Iq @ 1 kHz)
Figure 7. Normalized RDS(ON) vs.Junction Temperature (typical value)
R DS(ON) / (RD S(ON) @ 25 C) 1.8
1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0 20 40
fSW [kHz]
1.6
1.4
1.2
1.0
0.8
60
80
100
0
20
40
60
80
100
120
140
Tj [C]
Figure 5. Typical Low-Side R DS(ON) vs. Supply Voltage
RDS(ON) [] 0.300 0.296
Tj = 25C
Figure 8. Typical Drain-Source Diode Forward ON Characteristic
ISD [A]
3.0 Tj = 25C 2.5 2.0 1.5 1.0 0.5 0.0
0.292 0.288 0.284 0.280 0.276 0 5 10 15 V S [V] 20 25 30
700
800
900
1000
VSD [mV]
1100
1200
1300
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L6208
CIRCUIT DESCRIPTION The L6208 is a fully integrated bipolar stepper motor driver with two full bridge having power DMOS with a typical RDSON of 0.3 each. All the circuitry to implement the phase generation (decoding logic) is integrated, as well as a constant Toff PWM control for the current, separately for any of the two winding of the driven motor. The decoding logic generates three different sequences, selected by the HALF/FULL input. These are normal (two phases ), wave drive (one phase energized) and half-step (alternately one phase/two phases energized). The decoding logic generates three different sequences, selected by the HALF/FULL input. These are normal (two phases energized), wave drive (one phase energized) and half-step (alternately one phase/two phases energized). The constant Toff PWM current control consists in a sense comparator and a monostable.
When the current in each phase of the motor reaches the value set by the correspondent V voltage (Vref / RSENSE), ref it will be forced to decrease for a constant Toff time, set by the RC network applied to the RC and RCB pins. If the A Control pin is at a High logic level, during the off-time the voltage applied to the motor phase will be approx. 0 V, turning on the high-side MOSFETs of the bridge (slow decay recirculation ); if control is Low, instead, the voltage applied to the phase will be reversed, turning off the low side MOSFET that was on and turning on the opposite low-side (fast decay recirculation ).
Figure 9.
VS VS VS
On Time
Off Time in Slow-Decay Recirculation
Off Time in Fast-Decay Recirculation
Figure 10. PWM Chopping Current Control IOUT
TON Vref / RSENSE
Threshold
TOFF
(Recirculation)
t
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L6208
A non-dissipative current sensing on the high side power DMOSs, an internal reference and an internal open drain, with a pull down capability of 4mA (typical value), that goes LOW under fault conditions, ensure a protection against short circuit to GND or between two phases of each of the two full bridges. The trip point of this protection is internally set at 5.6 A (typ. value). By using an external R-C on the EN pins, the off time before recover normal operation conditions after a fault can be easily programmed, by means of the accurate threshold of the logic inputs. Note that protection against short to the supply rail is typically provided by the PWM current control circuitry. These features make the L6208 a complete bipolar stepper motor driver that outperforms the components currently available on the market
MOTOR DRIVING PHASE SEQUENCE The decoding logic integrated in the L6208 generates the sequences for normal drive, wave drive and half step modes. The state machine sequences and the output currents (neglecting, for simplicity, the PWM control) are shown below, in the case of clockwise rotation. For counterclockwise rotation the sequences are simply reversed. The state machine advances on the rising edge of the Clock signal, and a Low logic level on the Reset input restores the logic to state 1. HALF STEP MODE Half step mode is selected by a high logic level on the HALF/FULL pin.
Figure 11. IOUT1A
IOUT2A 3 4 5
2
6
IOUT1B
1
8
7 IOUT2B
Clock
1
2
3
4
5
6
7
8
10/15
L6208
NORMAL DRIVE MODE (Full-step two-phase-on) Normal drive mode is selected by a Low level on the HALF/FULL input when the state machine is at an odd numbered state.
Figure 12. IOUT1A
IOUT2A 3 4 5
2
6
IOUT1B
1
8
7 IOUT2B
Clock
1
3
5
7
1
3
5
7
WAVE DRIVE MODE (Full-step one-phase-on) Wave drive mode is selected by a Low level on the HALF/FULL input when the state machine is at an even numbered state.
Figure 13. IOUT1A
3
4
5 IOUT2A
2
6 IOUT1B
1
8
7 IOUT2B
Clock
2
4
6
8
2
4
6
8
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L6208
DIM. MIN. A A1 A2 B B1 c D E e E1 e1 L M 3.180 6.350 0.410 1.400 0.200 31.62 7.620 0.380
mm TYP. MAX. 4.320 0.015 3.300 0.460 1.520 0.250 31.75 0.510 1.650 0.300 31.88 8.260 2.54 6.600 7.620 3.430 0.125 6.860 0.250 0.016 0.055 0.008 1.245 0.300 MIN.
inch TYP. MAX. 0.170
OUTLINE AND MECHANICAL DATA
0.130 0.018 0.060 0.010 1.250 0.020 0.065 0.012 1.255 0.325 0.100 0.260 0.300 0.135 0.270
Powerdip 24
0 min, 15 max.
E1
A2
A
L B B1 e
A1
e1
D
24
13 c
1
12 M
SDIP24L
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L6208
DIM. MIN. A A1 A2 B C D E e H h k L 0.40 10.0 0.25 0.33 0.23 15.20 7.40 2.35 0.10
mm TYP. MAX. 2.65 0.30 2.55 0.51 0.32 15.60 7.60 1.27 10.65 0.75 0.394 0.010 0.013 0.009 0.598 0.291 MIN. 0.093 0.004
inch TYP. MAX. 0.104 0.012 0.100 0.0200 0.013 0.614 0.299 0,050 0.419 0.030
OUTLINE AND MECHANICAL DATA
0 (min.), 8 (max.) 1.27 0.016 0.050
SO24
h x 45
A2 A
0.10mm .004 Seating Plane
B
e
A1
K L H
A1
C
D
24
13
1
12
SO24
E
13/15
L6208
mm TYP. inch TYP.
DIM. A a1 a2 a3 b c D (1) D1 E e e3 E1 (1) E2 E3 E4 G H h L N S
MIN. 0.10 0 0.22 0.23 15.80 9.40 13.90
MAX. 3.60 0.30 3.30 0.10 0.38 0.32 16.00 9.80 14.50
MIN. 0.004 0 0.008 0.009 0.622 0.370 0.547
MAX. 0.141 0.012 0.130 0.004 0.015 0.012 0.630 0.385 0.570
OUTLINE AND MECHANICAL DATA
0.65 11.05 10.90 5.80 2.90 0 15.50 0.80 11.10 0.429 2.90 6.20 0.228 3.20 0.114 0.10 0 15.90 0.610 1.10 1.10 0.031 10(max.) 8 (max.)
0.0256 0.435 0.437 0.114 0.244 0.126 0.004 0.626 0.043 0.043
PowerSO36
(1): "D" and "E1" do not include mold flash or protrusions - Mold flash or protrusions shall not exceed 0.15mm (0.006 inch) - Critical dimensions are "a3", "E" and "G".
N
N a2 A DETAIL A e3 H D a3
36 19
A DETAIL B a1 E DETAIL A
c
e
lead
slug BOTTOM VIEW E3
B E2 E1 DETAIL B
0.35
D1
1
1
8
Gage Plane
-C-
S h x 45 b
0.12
M
L
SEATING PLANE G C
AB
PSO36MEC
(COPLANARITY)
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L6208
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. N o license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (R) 2001 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http:/ /www.st.com
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